Expert Modules

Deep dive into modern GPU architectures optimized for machine learning, from latest datacenter GPUs to next-generation designs

Develop high-fidelity simulators and performance models for evaluating next-generation AI accelerator architectures

Master the techniques for profiling, characterizing, and optimizing deep learning workloads across different hardware platforms

What MLPerf Inference/Training measure, how to read QPS/latency/accuracy, and pragmatic usage for architecture evaluation

SRE and platform engineering for ML training/serving clusters: resource allocation, gang scheduling, and system-level optimization

SRE and platform engineering for ML training/serving clusters: resource allocation, gang scheduling, and system-level optimization

Master the design principles of custom AI accelerators, from tensor processing units to emerging neuromorphic architectures

Design and optimization of high-performance interconnects for distributed AI training and inference systems

TTFT vs tokens/s optimization, batching strategies, KV-cache memory management, PagedAttention/vLLM impact, and practical serving tactics

Strategic simulation methodology: choose the right simulation paradigm and fidelity level; ask targeted questions, validate against reality

Master the design and optimization of distributed AI training systems across hundreds of nodes and GPUs

Comprehensive analysis of multimodal foundation model architectures, training methodologies, and system engineering challenges for vision-language AI systems

Translate simulated activity into power/thermal behavior and communicate perf/W trade-offs credibly using McPAT and HotSpot

Master Performance, Power, and Area analysis techniques for evaluating hardware design trade-offs in AI accelerators

Master queueing theory fundamentals and advanced techniques for analyzing performance, tail latency, and congestion control in modern computer systems, from CPU pipelines to datacenter-scale networks

Cut simulation time while bounding error and preserving phase behavior through systematic sampling methodologies

End-to-end reasoning about compute + data pathologies with evidence-based fixes for CPU pipelines, GPU occupancy, and memory hierarchies

Design for tails, not means: queueing theory, amplification effects, and tail-tolerant distributed system patterns

Turn counters and simple models into clear diagnoses and action items using systematic performance analysis methodologies

Deep dive into optimizing hardware architectures for transformer-based models, from attention mechanisms to large language model inference

Cross-validate models with real counters, quantify uncertainty, and communicate limits in performance analysis